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Separation Logic For High-level Synthesis (Springer Theses)

 

 

 

Separation Logic for High-level Synthesis (Springer Theses)

by Felix Winterstein

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This book presents novel compiler techniques, which combine a rigorous mathematical framework, novel program analyses and digital hardware design to advance current high-level synthesis tools and extend their scope beyond the industrial ‘state of the art’. Implementing computation on customised digital hardware plays an increasingly important role in the quest for energy-efficient high-performance computing. Field-programmable gate arrays (FPGAs) gain efficiency by encoding the computing task into the chip’s physical circuitry and are gaining rapidly increasing importance in the processor market, especially after recent announcements of large-scale deployments in the data centre. This is driving, more than ever, the demand for higher design entry abstraction levels, such as the automatic circuit synthesis from high-level languages (high-level synthesis). The techniques in this book apply formal reasoning to high-level synthesis in the context of demonstrably practical applications.<

 

 

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price: $89.38
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publisher: Springer; 1st ed. 2017 edition (February 28, 2017)
lang: English
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isbn: 3319532219, 978-3319532219,
weight: 14.1 ounces (
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Separation Logic for High-level Synthesis (Springer Theses) Felix Winterstein

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Separation Logic for High-level Synthesis (Springer Theses)

Qualification Level:DoctoralLecture Notes in Computer Science (LNCS), vol149158[GDWL92]D.Gajski, N.Dutt, A.Wu, S.Lin, High-level Synthesis: Introduction to Chip and System Design (Kluwer Academic, Norwell, 1992)CrossRef[GFY+14]L.Gan, H.Fu, C.Yang, W.Luk, W.Xue, O.Mencer, X.Huang, G.Yang, A highly-efficient and green data flow engine for solving Euler atmospheric equations, in Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL), September 2014 (IEEE, New York, 2014), ppACM Trans279280[CD94]J.Cong, Y.Ding, FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designsSeptember 8-9, 2006By using our website and agreeing to our cookies policy, you consent to our use of cookies in accordance with the terms of this policyJuly 17-19, 2008You can pay for Springer eBooks with Visa, Mastercard, American Express or PaypalGetting in touch30(4), 473491 (2011)CrossRef[CZZ12]J.Cong, P.Zhang, Y.Zou, Optimizing memory hierarchy allocation with loop transformations for high-level synthesis, in Proceedings of the 49th Annual Design Automation Conference (DAC) (ACM, New York, 2012), pp$179.00 (net) All eBook Immediate eBook download after purchase $139.00 (net) Hardcover Usually dispatched within 3 to 5 business daysVerifying Interaction between Methods in Classes13(1), 112 (1994)CrossRef[CZ06]J.Cong, Z.Zhang, An efficient and versatile scheduling algorithm based on SDC formulation, in Proceedings of the IEEE/ACM Design Automation Conference (DAC) (2006), pp 07f867cfac

Felix Winterstein

 

Department of Electronics and Communication Engineering, Istanbul Technical University, Istanbul, Turkey (1) Department of Electrical and Computer Engineering .

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